1. Field of the Invention
The present invention relates generally to the field of high speed data transfer, and more specifically to managing virtually concatenated payloads in specific data transfer architectures, such as SONET/SDH.
2. Description of the Related Art
Data communication networks receive and transmit ever increasing amounts of data. Data is transmitted from an originator or requester through a network to a destination, such as a router, switching platform, other network, or application. Along this path may be multiple transfer points, such as hardware routers, that receive data typically in the form of packets or data frames. At each transfer point data must be routed to the next point in the network in a rapid and efficient manner.
Data transmission over fiber optics networks may conform to the SONET and/or SDH standards. SONET and SDH are a set of related standards for synchronous data transmission over fiber optic networks. SONET is short for Synchronous Optical NETwork and SDH is an acronym for Synchronous Digital Hierarchy. SONET is the United States version of the standard published by the American National Standards Institute (ANSI). SDH is the international version of the standard published by the International Telecommunications Union (ITU). As used herein, the SONET/SDH concepts are more fully detailed in various ANSI and ITU standards, including but not limited to the discussion of concatenated payloads, ITU-T G.707 2000, T1.105-2001 (draft), and T1.105.02-1995.
The virtual concatenation standard for SONET/SDH defines a maximum differential delay compensation range of 2048 frames, where differential delay compensation is the amount of time compensation required to keep a large number of concatenated channels aligned. For 10 Gbps traffic, 2048 frames of data translate to 320 Mbytes of data. Given this relatively large size, typical SRAMs (static random access memories) cannot store this data. SDRAM, synchronous dynamic random access memory, available in large number of bytes, is the preferred choice for performing differential delay compensation on these relatively large amounts of data.
However, SDRAM has high latency for read and write accesses when accessing different rows of the same bank. As 10 Gbps reading and 10 Gbps writing bandwidths are required to support differential delay compensation for virtual concatenation in SONET/SDH, and the maximum bandwidth available, without considering latency, in 166 MHz DDR SDRAM with 64-bit bus width is only 21.248 Gbps, the required access efficiency using 166 MHz DDR SDRAM memory for 10 Gpbs traffic is very high. Many previous methods for decreasing latency are not sufficiently effective for use in very high-speed networking applications using SDRAM in virtual concatenation applications.
A design that uses high speed SDRAM, such as 166 MHz DDR SDRAM, in processing virtual concatenation payloads using differential delay compensation compliant with SONET/SDH standards and that minimizes latency in such processing may provide advantageous qualities over previously known designs, including designs compliant with the SONET/SDH architecture.